POWER METHODOLOGY/DESIGN ENGINEER Job in Santa Clara, California US
POWER METHODOLOGY / DESIGN ENGINEER #1343820
RESPONSIBILITIES:
- Power integrity analysis and methodology development on large scale chips
- Power model generation for custom circuit blocks.
- Working with Package and Signal Integrity teams to model and analyze chip level power noise.
- Working with Clock team to model and analyze power noise implications on clocks.
MINIMUM REQUIREMENTS:
- BS/MS in Electrical or Computer Engineering with 3+ years of experience.
- Good understanding of deep submicron process issues and circuit design is required
- Hands on experience in design and analysis of low power circuits, e.g. power gating, decaps, multi-vt
- Hands on experience in power integrity analysis at gate level and transistor level e.g. voltage drop, power EM.
- Expertise on industry standard Power Integrity tools e.g. Apache Redhawk, Encounter Power System (EPS) etc.
- Understanding of timing and power modeling of standard cells, RAMs, and custom circuits required.
- Hands on experience running Spice is required.
- Understanding of clock networks or package design is a definite plus.
- Proficiency in scripting language, such as, Perl, Tcl, Make and automation methods/algorithms a certain plus.
EOE
Interested in talking with us? Please apply directly at NVIDIA.COM