Chip/Package Co-Design Methodology Engineer (f/m) Job in Villach (At), Steiermark Austria
Job Description:
As a methodology engineer (f/m) you will be responsible for the development of parts of Infineon's internal chip/package co-design flow and methodology.
This includes:
- Requirement collection, analysis and methodology definition-based inputs of our internal chip and package designers
- Evaluation of EDA tools and their features
- Definition, specification and implementation of script enhancements inside the EDA tools or the environment within Linux and Windows
- Coordination of feature/software development activities at EDA vendors or outsource partners
- Overall flow and methodology test and QA
- Tool, methodology, and flow roll-out within Infineon worldwide, user training, and project support
In particular you will be responsible for the development of our new chip/package co-design flow for leadframe packages, which bridges the gap between mechanical CAD (package design environment in AutoCAD) and electrical CAD (chip design environment in Cadence Virtuoso or Cadence Encounter), including connectivity entry, physical layout design of the leadframe and the bonding diagram, DRC, LVS, and the link to electrical and thermal simulation of the complete system of chip and package.
This position is subject to the collective agreement for workers and employees in the electrical and electronics industry, employment group G (http://www.feei.at/kollektivvertraege/kv_tabelle/). A higher payment is negotiable depending on your expertise and skills.