Digital Verification Engineer Job in Manchester 03103, New Hampshire US
What You Will Do:
As Allegro Microsystems continues to architect, design and deploy its mixed signal devices the digital content continues to increase. As an Digital Verification Engineer (entry-level or experienced), you will have the opportunity to contribute within the framework of an experienced and expanding Digital group. We're looking for a motivated individual that can leverage the group's experience to begin quickly contributing to the success of the team.
Your primary focus will be the use and design of constrained random test benches for verification. Typical tasks include:
- Generation of test plans based on design requirements and product data sheets
- Development of bus-functional models for verification of custom or industry-standard interfaces
- Writing of tests to target specific functionality at the bus level or system level
Analysis of test results, test coverage and debug of unexpected design behavior - Script generation for processing results as well as regression control configuration
- Writing and/or debug of programs in C or C++ for behavioral models in mixed signal test environment
Education and Experience Requirements
The successful candidate will possess a Bachelor's / Masters degree in Electrical Engineering - Entry level with 3.0+ GPA or up to 5 years experience. Excellent communication, documentation, problem-solving and analytical skills are required.
Allegro has an extremely diverse product base. As new products are designed each new test environment will be written in System Verilog and will follow the Universal Verification Methodology (UVM). Exposure to a higher level, object oriented language is highly desired, as is exposure to one of the structured verification methodologies.
Experience with the use of the following is a plus: Verilog, System Verilog, Synthesis, DFT, OVM, UVM, VMM, PERL, C, C++, UNIX/LINUX, FPGA Design and implementation.
