Engineer, Senior Digital IC design Job in Santa Clara 94067, California US
Marvell. Moving Forward Faster.
Marvell offers revolutionary devices that touch every point of the communications infrastructure: switching, transceivers, wireless, PC connectivity, communications controllers, and storage. Our continuous cycle of innovations has enabled Marvell to consistently deliver the industry’s gold standard, emerging as the market leader in virtually all of our product categories.
Position Description:
Design and develop high-speed and low power digital circuits for the digital signal processing core of the read channel transceiver using state-of-the-art IC design methodologies, design flows, and innovative circuit technologies.
* Design high-speed data paths and control logic to implement arithmetic functions and signal processing algorithms..
* Develop RTL code for control blocks
* Design Schematics for Semi-Custom blocks for Signal processing units.
* Perform functional verification of designs on block and chip level.
* Run Synthesis for RTL blocks, run timing analysis and functional and formal verification for blocks.
* Develop test benches for block level simulations and run functional verification on the chip level
* Run timing verification on block level and chip level and be able to debug and fix timing issues
* Help in integrating the design in chip level and be able to work with other designers to define, verify and debug interface signals.
* Be able to work with system validation team to debug issues related to the block on silicon
* Oversee and guide layout and physical verification activities for PR and timing closure .
* Contribute test specifications and support evaluation of the design in coordination with application and product engineering.
* Provide design documentation, descriptions and information to application engineers, field application engineers, product engineers, and customers.
To Apply Visit Marvell Semiconductor
Qualifications:
The ideal candidate is familiar with digital, digital and mixed-signal IC design methodologies, understands all stages of ASIC and mixed-signal design flows, and is experienced in the usage of state-of-the-art design tools. This candidate is strong in RTL coding, logic design, synthesis, timing analysis and verification, demonstrates at least basic knowledge of deep sub-micron CMOS technologies and device physics, understands digital signal processing algorithms, and has solid knowledge of related VLSI architectures.
Minimum requirements are:
* Knowledge of hardware description languages and experience in behavioral and RTL coding (Verilog preferred).
* Knowledge of STATE machine design and synthesis.
* Knowledge of mixed signal simulation, SPICE.
* Skilled in design verification, logic simulation and formal verification.
* Proficient in Synopsys synthesis and timing tools, design complier, primetime etc.
* Good knowledge DFT concepts.
* Knowledge of Place and Route and timing closure flows.
* Knowledge of computer arithmetic, digital signal processing and related VLSI architectures.
* MS in Electrical Engineering and at least two years of professional experience.
Founded in 1995, Marvell Technology Group Ltd. has operations worldwide and approximately 5,000 employees. Marvell's U.S. operating subsidiary is based in Santa Clara, California and Marvell has international design centers located in the U.S., Europe, Israel, Singapore and China. A leading fabless semiconductor company, Marvell ships over one billion chips a year.