Engineer, Senior Physical Design Job in Santa Clara 94067, California Us
Marvell. Moving Forward Faster.
Marvell offers revolutionary devices that touch every point of the communications infrastructure: switching, transceivers, wireless, PC connectivity, communications controllers, and storage. Our continuous cycle of innovations has enabled Marvell to consistently deliver the industry’s gold standard, emerging as the market leader in virtually all of our product categories.
Position Description:
The person will responsible for chip top level integration support for different SOC under tight project schedule. It requires strong knowledge on various issues on backend design flow to achieve high efficiency and reliability of result.
Experienced in chip top integration. Good communication skills and experiences with back-end layout verification tool (Calibre) and Layout editor. Prefer in experience with Place and Route tool(ICC, Astro).
To Apply Visit Marvell Semiconductor
Qualifications:
Experienced in chip top integration. Good communication skills and experiences with back-end layout verification tool (Calibre) and Layout editor. Prefer in experience with Place and Route tool(ICC, Astro).
The candidate will have a BS Degree or diploma of layout training course.
Understanding detailed layout of transistor,resistor,capacitor and diode.
Understanding of analog layout such as device matching, common-centroid,P/G rail separaton, wire shielding, cross-coupling.
Must be familiar with DRC/LVS verification tools.
Must be familiar with Unix OS. Experience with Candence or Silicon Canvas layout tools is a plus.
Founded in 1995, Marvell Technology Group Ltd. has operations worldwide and approximately 5,000 employees. Marvell's U.S. operating subsidiary is based in Santa Clara, California and Marvell has international design centers located in the U.S., Europe, Israel, Singapore and China. A leading fabless semiconductor company, Marvell ships over one billion chips a year.