LEAD ASIC INTEGRATION ENGINEER Job in Santa Clara, California Us
LEAD ASIC-PD INTEGRATION ENGINEER #1427017
As a senior member of our ASIC-PD (Physical Design) team, you'll be leading the physical integration efforts for some of our most challenging GPUs. In this role, you are responsible for taking the logical unit designs and creating a physically realizable full chip design. This includes such tasks as partitioning, floorplanning at the full chip level, ensuring netlist quality, ECO generation, creating static timing constraints, and performing static timing analysis/closure. In this role you will be interfacing with many engineering groups including RTL design, package design, DfT, and place and route.
RESPONSIBILITIES:
- Create full chip floorplans
- Full chip netlist generation
- Static timing constraint generation/analysis/closure
- Assist in flow development for chip integration and static timing analysis
- Lead final timing closure effort
MINIMUM REQUIREMENTS:
- BS or MS in Electrical Engineering or Computer Science
- 7 - 10 years of relevant ASIC design experience with a focus in chip integration and static timing analysis
- Strong knowledge of ASIC design flows from RTL through tapeout
- Experience with 40nm or smaller process technology
- Full chip integration experience
EOE
Interested in talking with us? Please apply directly at NVIDIA.COM