Manager / Principal Design Engineer (ASIC) Job in Sunnyvale 94089, California US
4165_Manager / Principal Design Engineer (ASIC)
Location: Sunnyvale, CA
Primary Job Responsibilities:
ASIC Manager/Principal Design Engineer is a versatile front end position and will be responsible for taking complex SOCs to production. Manage all aspects of the SOC from Architecture to production for APM transport division. Guide the design team to resolve all silicon issue. Interface with Software, Validation, FAE and Marketing teams and manage all SOC related queries coming from these groups. Manage a team of Engineers based in various geographic locations such as India (Pune), Vietnam (Ho Chi Ming City) and US (Sunnyvale).
Education/Experience Requirement:
· BSEE/MSEE or higher
· Expert in Verilog RTL design / System Verilog and UVM methodology
· 10+ years work experience in designing and/or Validation of complex SOCs with at least 2 yrs experience managing teams and projects.
· Knowledge of PCIE-Gen2.0/3.0, Ethernet. (10Gig/1Gig) required
· Familiar with debug of embedded SOCs [ARM] and should have worked on lab bringup of a complex SOC with multiple interfaces like PCIE,DDR.
· Familiar with high speed serdes technologies and debug/characterization of the same.