Physical Design Engineer Job in San Jose, California US

Physical Design Engineer

Apply Now See all jobs at this company Printer-Friendly Version | Save this job | Email this job Physical Design Engineer Apply Now Job Overview Company: Aerotek Job Type: Engineering Base Pay: N/A Other Pay: Based on Experience Employee Type: Full-Time Manages Others: Not Specified Relocation Covered: Not Specified Industry: Computer Hardware Reference ID: 2515191 Required Education: Not Specified Required Experience: Not Specified Required Travel: Not Specified Location: San Jose, CA 95119 ( Map it! ) Loading map ... Job Description Job Classification: Contract INDUSTRY PROFESSIONAL EXPERIENCED ENGINEERS ONLY! Experience at INTEL, AMD, and MARVELL - HIGHLY DESIRABLE COLLEGE PROJECTS - DO NOT APPLY Position Title: Physical Design Engineer Duration: 12- 18 months (future opportunities for more work likely to follow) Agreement in place: Yes Interview Date(s): Can interview within two days after internal interview at Aerotek Travel: None Start Date: ASAP Drug and/or Background: Yes US Citizenship Requirements: NA Top 3 "must haves" for this position?: 1. Chip Level Planning, Routing, 2. SoC experience, Physical Design Integration (PDI) Experience 3. Experience with Press and rout (PNR or PR) "Wish List" skills: 1. Experience with 32nm, 45nm and/or 65 nm SoC KEY RESPONSIBILITIES: - Tasks to include Chip Level Floor planning, Bus / Pin Planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification and Sign Off - Identify complex technical problems, break them down, summarize multiple possible solutions, and lead the team in the right direction - Drive and hands-on flow development and scripting - Technical and schedule discussion with multi-site engineers and managers - Lead projects from specification development to final product. REQUIREMENTS: - Over 8 years experience with MSEE or MSCE in ASIC Physical Design from RTL to GDSII - Excellent analytical and problem solving skills along with attention to details - Strong Timing closure skills including signal integrity, RC extraction, Clock tree synthesis, and library understanding - Hands on experience in taping out 32nm, 45nm, and/or 65nm SOC - Understanding of VLSI Design and working experience on CAD tools from Synopsys, Cadence and Mentor Graphics - Strong written and verbal communication skills. Time Management, and Presentation Skills - Must be a self-starter, and be able to independently and efficiently drive tasks to completion - Must be very team oriented, will be working with team of 30 - Ability to provide mentorship and guidance to junior and senior engineers, and be an effective team player - IO Design and external interface timing. All ASIC backend flows from design to tape out. - SOC Lead for Floorplan, time budgeting, top level timing closure and chip PR - Knowledge of digital, analog and mixed signal IC design. - GPU Physical design projects ++++ / Fusion projects Join Aerotek, one of the leading providers of engineering and engineering support professionals in North America. Due to our growth, we're constantly on the lookout for qualified professionals to place in contract, contract-to-hire, and permanent placement positions across a number of different industries. We know it's more than just your day-to-day responsibilities that can make or break a job. It's the support you get. That's the reason Aerotek offers a variety of benefits including medical, dental, optical, 401k, and many more. Don't put your career in the hands of just anyone, put it in the hands of a specialist. Join the Aerotek team! Allegis Group and its subsidiaries are equal opportunity employers and will consider all applications without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability or any other characteristic protected by law. Job Requirements Physical Design, CHIP DESIGN, Place and Route, Tape out Apply Now