PHYSICAL IMPLEMENTATION ENGINEER Job in Santa Clara, California Us
PHYSICAL IMPLEMENTATION ENGINEER #1397602
RESPONSIBILITIES:
- Responsible for all aspects of physical design and implementation of Graphics processors, integrated chipsets and other ASICs targeted at the desktop, laptop, workstation, set-top box and home networking markets.
- Participate in physical design, translating behavioral code into optimal gate level and/or circuit level design. Use of PR tools and flows for physical implementation and timing closure. Analyze timing, power and noise and back-end verification of functional blocks.
- Design of structured data paths, optimize circuit behavior to meet performance, area and power targets.
MINIMUM REQUIREMENTS:
- BSEE required, MSEE preferred
- 3+ years of experience in large VLSI physical design implementation and methodologies for processes 40nm or smaller.
- Solid background in VLSI circuit design skills. Circuit level comprehension of critical path analysis, power and noise issues.
- Working knowledge of deep sub-micron routing issues as they relate to power and timing.
- Must be proficient in PR and timing analysis CAD tools from Magma (Talus / Quartz), Synopsys (ICC / dc_shell / pt_shell / STAR-RC), Cadence (FE / Nanoroute), Nanotime, Spice
- Proficiency using Perl, TCL, Scheme, Make scripting is preferred
EOE
Interested in talking with us? Please apply directly at NVIDIA.COM