SENIOR ASIC TIMING ENGINEER Job in Beaverton, Oregon Us
SENIOR ASIC TIMING ENGINEER #1349882
RESPONSIBILITIES:
- Timing signoff and convergence of large-scale high-frequency low-power designs at block level and full chip level.
- Own full aspect of timing from RTL to gds2, including effective RTL coding/synthesis strategies, timing constraints generation, physical/timing convergence, and ECO implementation.
MINIMUM REQUIREMENTS:
- BS in Electrical or Computer Engineering + 5 yrs experience in Timing
- Hands-on expertise and experience in full-chip Static Timing Analysis, timing constraints generation and management, and timing convergence of large SoCs / ASICs required.
- Good understanding of ASIC/hardware design, and hands-on skills in RTL/Logic design for timing closure, logic synthesis, equivalence checking required.
- Expertise in physical design aspect of timing closure and closing timing by improving placement, routing, cell sizing, buffering, logic optimization, etc. needed.
- Understanding of DFT logic structures, and hands-on experience with DFT timing closure w.r.t scan shift and capture, transition faults, boundary scan, BIST, etc. required.
- Expertise in analyzing and converging on crosstalk delay, noise glitch, and electrical rules in deep-sub micron processes required.
- Understanding of process variation effects, and experience in variations analysis/modeling techniques and convergence mechanism would be a plus
- Experience with transistor level circuits/physical design issues and transistor level STA would be a plus.
- Expertise and in-depth knowledge of industry standard EDA tools (Timing, Synthesis, SPICE) required.
- Proficiency in scripting language, such as, Perl, Tcl, make required. Experience in methodology or flow development/automation would be a plus.
EOE
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