SENIOR TAPEOUT MASK DESIGN ENGINEER Job in Santa Clara, California Us
SENIOR TAPEOUT MASK DESIGN ENGINEER #1382035
RESPONSIBILITIES:
- Job responsibilities will include integrating and verifying fullchip layouts.
- Use common industry standard layout design tools (Virtuoso) and verification suites (Cadence and Synopsys).
- Should also have experience working closely with circuit designers to perform custom layout of complex designs as well as novel testchip structures.
MINIMUM REQUIREMENTS
- Formal layout design education, diploma required.
- 3+ years of relevant layout experience in deep submicron CMOS process.
- Experience with fullchip verification.
- Ability to independently draw and verify complex layouts using tools.
- Experience using Cadence Virtuoso, Calibre DRC / LVS or Hercules DRC / LVS or Mohave verification tools.
- Knowledge of skill programming, PCELL generation, auto router is a plus.
- A self-motivated, team player with good communication skills.
- A good track record of on time work delivery is a must.
- Currently considering local / full time candidates only.
EOE
Interested in talking with us? Please apply directly at NVIDIA.COM