SR. MASK LAYOUT DESIGNER Job in Shanghai, Shanghai China

SENIOR MASK LAYOUT DESIGNER #1463277

RESPONSIBILITIES:
- Perform physical layout for standard cells, embedded SRAM macros and custom modules in deep sub-micron CMOS process.
- Cell level and macro level layout floor-planning
- Layout verification including LVS, DRC and ERC.
- Layout data version control and frame-view generation.

MINIMUM REQUIREMENTS:
- BSEE or equivalent.
- Over 2 years related experience.
- Familiar with Cadence design environment.
- Proficient in physical verification (DRC/LVS) tool.
- Knowledge of CMOS transistor devices.
- Knowledge of UNIX system and commands.
- Place and Route knowledge is a plus.

Interested in talking with us? Please apply directly at NVIDIA.COM