Principal Verification Engineer – OVM – UVM
Skills Required: Design Verification, SystemVerilog, OVM, UVM, VMM, SystemC, C++, SONET, OTN, Ethernet Job Description: Principal Verification Engineer – Growing IPO Bound IC Startup – OVM/UVMWe are a Well-Funded, VC-Backed, Award Winning, and Exciting Pre-IPO startup that is IPO bound. Because of our recent successes with high-speed SoCs, we are currently ramping up and looking to add a Staff or Principal Verification Engineer to develop leading edge verification methodologies.If you are a Staff or Principal Verification Engineer that has strong SystemVerilog Read more […]
July 18, 2007
• Tags: California Us, High Speed SoCs Job in Mountain View 94035, OVM, Principal Verification Engineer, UVM • Posted in: General • Comments Off on Principal Verification Engineer – OVM – UVM