LEAD ASIC INTEGRATION ENGINEER Job in Santa Clara, California Us

LEAD ASIC-PD INTEGRATION ENGINEER #1427017As a senior member of our ASIC-PD (Physical Design) team, you’ll be leading the physical integration efforts for some of our most challenging GPUs. In this role, you are responsible for taking the logical unit designs and creating a physically realizable full chip design. This includes such tasks as partitioning, floorplanning at the full chip level, ensuring netlist quality, ECO generation, creating static timing constraints, and performing static timing analysis/closure. In this role you will be interfacing with many engineering groups including RTL design, Read more […]

January 24, 2010 • Tags: , • Posted in: General • Comments Off on LEAD ASIC INTEGRATION ENGINEER Job in Santa Clara, California Us