SENIOR ASIC TIMING ENGINEER Job in Austin, Texas Us
SENIOR ASIC TIMING ENGINEER #1369455In this role you will be responsible for developing static timing analysis (STA) constraints, running full chip and partition level STA, and generating appropriate timing ECOs for the design. As part of our global team, you will be expected to help contribute to improvement of our overall methodologies and flows. In addition to STA tasks, you may also be required to perform synthesis, formal verification (equivalence), and netlist quality checks. MINIMUM REQUIREMENTS:- BS in Electrical or Computer Engineering 5+ yrs experience in static timing analysis. – Expertise Read more […]
December 4, 2010
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