Design Engineer Job in Toronto, Ontario Canada
Location : Toronto
RESPONSIBILITIES:
The candidate will be responsible for defining the architecture, micro-architecture and detailed design of complex SoC sub-systems and modules. The candidate will have to work closely with the software and system engineering groups to make good engineering and business trade-offs between performance, schedule and risk. In addition to their daily engineering work, they may also be expected to help with maintaining schedules, and to be involved with document and code reviews. Skills/Experience Knowledge of ASIC design flow covering all phases of the design cycle including architecture and design specification, RTL coding, verification, synthesis, formal verification and static timing analysis
Strong skills in RTL logic design, Verilog coding, synthesis, and verification.
Experience with cross clock domain designs
Expertise in writing technical specifications
Excellent written and oral communication skills
Working experience with some of the following: Ethernet, PCI, USB, Amba, ARM or MIPS processors, DMA, etc.
Experience with writing embedded software in C/C++ or assembly language
REQUIREMENTS:
BS (MS desired) in Electrical or Computer Engineering desired
Experience with Synopsys design tools for simulation, synthesis, static timing analysis and equivalence checking
Experience with coverage driven verification including functional verification utilizing industry standard verification languages such Vera or SystemVerilog
Working experience with modeling using SystemC
Experience with telecommunications products and network protocols such as Ethernet, TCP/IP, routers, etc
Hands-on experience with chip bring-up, debug, and lab equipment such as logic analyzer, pattern generator, etc.
Experience with one or more scripting languages (Perl, TCL, Python, etc.)
Experience in SOC design involving embedded processors (preferably ARM knowledge), standard
Responsibilities Develop ASIC specification, architecture, and micro-architecture of SoC (System-on-Chip) and NoC (Network-on-Chip) sub-systems and modules
Provide design documentation for own blocks, and for blocks that are to be implemented by others
Implement designs in Verilog with minimal supervision
Perform design and code reviews
Design and execute simulations to verify block-level and chip-level functionality
Perform synthesis, gate level simulation, timing analysis, design for test, of multi-million gate ASICs
Assist in lab testing and post silicon debugging
For prompt consideration, please send your resume to fitz@huntech.com