MASK DESIGN ENGINEER Job in Santa Clara, California Us
MASK DESIGN ENGINEER #1424947
JOB DESCRIPTION / QUALIFICATIONS:
- Perform physical layout for standard cells, embedded SRAM macros and custom modules in deep sub-micron CMOS process.
- Cell level and macro level layout floor-planning
- Layout verification including LVS, DRC and ERC.
- Layout data version control and frame-view generation.
MINIMUM REQUIREMENTS:
- BSEE or up to 8 years of relevant experience.
- Familiar with Cadence design environment.
- Proficient in physical verification (DRC/LVS) tool.
- Knowledge of CMOS transistor devices.
- Knowledge of Unix system and commands.
- Place and Route knowledge a plus.
- Perl or unit shell programming a plus.
- Be a good team player with effective written and verbal communication skills.
EOE
Interested in talking with us? Please apply directly at NVIDIA.COM