MASK DESIGN ENGINEER Job in Santa Clara, California Us
MASK DESIGN ENGINEER #1424947JOB DESCRIPTION / QUALIFICATIONS:- Perform physical layout for standard cells, embedded SRAM macros and custom modules in deep sub-micron CMOS process.- Cell level and macro level layout floor-planning- Layout verification including LVS, DRC and ERC.- Layout data version control and frame-view generation.MINIMUM REQUIREMENTS:- BSEE or up to 8 years of relevant experience.- Familiar with Cadence design environment.- Proficient in physical verification (DRC/LVS) tool.- Knowledge of CMOS transistor devices.- Knowledge of Unix system and commands.- Place and Route knowledge Read more […]
June 9, 2010
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