Physical Design Engineer Job in Santa Clara, California US
Physical Design Engineer
Title: Physical Design Engineer Location: Santa Clara, CA Duration 6 - 12 mos You should possess a minimum of a Bachelor of Science in Electrical Engineering or Computer Engineering with at least 5 years of semiconductor manufacturing, design, or architectural experience. Master of Science degree in Electrical Engineering, Computer Engineering with at least 3 years of semiconductor manufacturing, design or architectural experience preferred. Minimum Skills and Experience Required: - 5 years of experience in ATPG tools preferably Mentor Graphics Tessent/Fastscan, scan insertion using DFT Compiler, scan design/architecture, and debug -5 years of experience in RTL/Gate Level verification and debug with Synopsys DVE/VCS and/or Modelsim. - 3 years of experience in writing scripts, like Perl/TCL. Preferred Skills and Experience - Demonstrated knowledge in the basic Design for Test, Design for Debug, and Design for Validation techniques. - Demonstrated knowledge in MOS analog circuits . - 3 year of experience in Verilog* and/or System Verilog (our RTLs are written in system verilog).