Principal RFIC Design Engineer Job in San Jose 95113, California US
We have a spectacular Bay Area Career Opportunity with growth potential a competitive compensation package! If you are ready for new challenges have the desire to lead the architecture design of RF/analog mixed signal designs, then send us your resume today! This is a full time, direct hire opportunity with a VERY successful company that will be actively shipping for revenue this year, giving the right candidate a "ground floor" opportunity to acquire private equity before this company is bought or IPO's!
This excellent and very senior level role will involve RFIC design, layout, verification of CMOS circuit blocks such as mixers, LNAs, amplifiers, PLLs, ADC/DACs, filters, dedicated analog processing circuits. You will have access to the state of the art lab for evaluation, measurement, and debugging of silicon, and will be charged with working with the management and design teams to communicate results. Also, as the Principal Design Engineer, you will verify circuits perform simulations utilizing AMS Designer, SpectreRF RFDE/Golden Gate in the Cadence IC design suite. You will also be charged with performing layout layout verification, using Virtuoso Assura tools.
The successful candidate will hold at least a MSEE degree, as well as, 10 or more years of RFIC Design experience. We are looking for a proven track record of designing CMOS RF/Analog circuits that have been manufactured in high volume production that are stable over process, voltage temperature corners; this includes a throughout knowledge of CMOS technology (DFM, device physics, manufacturing process, ESD), signal processing, and systems theory.
In addition, if you have:
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Confirmed experience in designing mentoring designers in wireless transceivers building blocks such as mixers, low noise amplifiers, oscillators, programmable baseband filters, data converters, biasing circuits, bandgap references, regulators, op-amps, PLL blocks;
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Excellent familiarity with SOC isolation techniques;
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Strong hands-on experience with Cadence based IC layout, parasitic extraction, resimulation verification of RF circuits;
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Experience with design for test approaches development of characterization production test plans;
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Strong hands-on experience in the lab with silicon evaluation, debugging, characterization, bring up;
If interested in this excellent opportunity, please send your resume in a word attachment to: Sam@ZanderMax.com
REFERRAL BONUS:
Do you know a friend or colleague who might be a great fit for this position? ZanderMax has the best referral bonus in the business! Refer a friend or colleague and when we place your referral at this position or any other, you will be handsomely rewarded with a referral bonus of up to $3,000!
Have a great day and we look forward to hearing from you soon!