Senior ASIC Design Verification Engineer Job in Los Altos 94022, California US
As the newest member of the Functional verification team, you will be responsible for the development of leading edge verification methodologies their timely successful deployment against innovative industry leading, coherent detection, OTN chip solutions at line rates of 100GHz beyond.
Qualifications:
- Previous ASIC verification experience
- Framer verification expertise with SONET or OTN
- Networking domain knowledge
- SystemC or C++ experience
- Pseudo-random, functional coverage verification methodologies
Desired:
- SystemVerilog SystemVerilog class libraries such as UVM, OVM or VMM
- Strong knowledge of DSP analog
- Experience with SVA, PSL or OVL assertions
- Experience with formal model checking tools
If interested in this excellent opportunity, please send your resume in a word attachment to: Sam@ZanderMax.com
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