Sr. Verification Engineer, ASIC, SystemVerilog, global leader Job in San Diego 92101, California Us

Skills Required:

ASIC Verification, SystemVerilog, System Verilog, VMM, OVM, Vera

Job Description:

We are the global leader in a rapidly growing space, working on the most cutting-edge technology available. As a top company in a fast growing industry, we have a great working environment where engineering is our top priority. We manage to keep a vibrant, startup-like environment where innovation and technology advancement occur on a daily basis. You will have the chance to shine as a top contributor and rise the ranks in a growing company while working in an exciting, technology space. The product you will be working on is a next generation product that will revolutionize the data storage space and get a chance to work on the most cutting-edge, modern verification methodologies and environments. We are located in Sunny Southern California in one of the best places to live and work in the world!

If you are a top-notch Senior Design Verification Engineer, Sr. Design/Verification or an ASIC Verification Engineer with strong System Verilog experience, please read on!

What's in it for you:

- Leading a top technical team on the most cutting edge technology around
- Work with the best and brightest in the industry
- High-visibility and excellent growth opportunity - including the possibility of taking over this group in a lead or management role
- Competitive salary top benefits and stock options

What you need for this position:

- BSEE 5+ years ASIC Verification experience (MSEE preferred)
- Strong verification with SystemVerilog based OVM / UVM, VMM or related methodology
- C / C++ Verilog experience
- Experience with embedded microprocessors (i.e. ARM, ARC, MIPS, PowerPC, etc)
- ECC (error correction code, LDPC, Reed-Solomon, etc.) data compression is a plus
- Previous ASIC design experience is a plus
- High-speed interface experience - i.e. SATA, SAS, PCIe, Fibre Channel, etc. is a plus
- Memory systems and Memory controller experience (i.e. DDR2, 3, etc.) is a plus
- SOC Architecture design and implementation knowledge
- Scripting language experience (i.e. Perl, Shell, Python)
- Experience with Flash Memory, SSD's, HDD's are a big plus.
algorithm experience is a big plus.
- HW behavioral modeling in SystemC, C/C++, etc is a plus.

What you'll be doing:

- Taking charge of development deployment of verification methodology
- Full responsibility of SystemVerilog / OVM models, test plans, generation of coverage matrices, constrained random verification environment, etc.
- Planning execution of system and block level verification
- Working with multi-disciplinary team (design, etc) to meet quality req's at system and block level
- Working with design architecture teams to understand functionality of logic blocks

So, if you are a top-notch Senior Design Verification Engineer, Sr. Design/Verification or an ASIC Verification Engineer with strong System Verilog experience, please apply today!

Must be authorized to work in the United States on a full-time basis for any employer.

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