POWER METHODOLOGY/DESIGN ENGINEER Job in Santa Clara, California Us
POWER METHODOLOGY / DESIGN ENGINEER #1343820RESPONSIBILITIES:- Power integrity analysis and methodology development on large scale chips – Power model generation for custom circuit blocks.- Working with Package and Signal Integrity teams to model and analyze chip level power noise.- Working with Clock team to model and analyze power noise implications on clocks.MINIMUM REQUIREMENTS:- BS/MS in Electrical or Computer Engineering with 3+ years of experience. – Good understanding of deep submicron process issues and circuit design is required- Hands on experience in design and analysis of low power Read more […]
POWER METHODOLOGY/DESIGN ENGINEER Job in Santa Clara, California US
POWER METHODOLOGY / DESIGN ENGINEER #1343820RESPONSIBILITIES:- Power integrity analysis and methodology development on large scale chips – Power model generation for custom circuit blocks.- Working with Package and Signal Integrity teams to model and analyze chip level power noise.- Working with Clock team to model and analyze power noise implications on clocks.MINIMUM REQUIREMENTS:- BS/MS in Electrical or Computer Engineering with 3+ years of experience. – Good understanding of deep submicron process issues and circuit design is required- Hands on experience in design and analysis of low power Read more […]