SENIOR ASIC TIMING ENGINEER Job in Beaverton, Oregon Us
SENIOR ASIC TIMING ENGINEER #1349882RESPONSIBILITIES:- Timing signoff and convergence of large-scale high-frequency low-power designs at block level and full chip level.- Own full aspect of timing from RTL to gds2, including effective RTL coding/synthesis strategies, timing constraints generation, physical/timing convergence, and ECO implementation.MINIMUM REQUIREMENTS:- BS in Electrical or Computer Engineering + 5 yrs experience in Timing – Hands-on expertise and experience in full-chip Static Timing Analysis, timing constraints generation and management, and timing convergence of large SoCs / Read more […]
December 4, 2008
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