SENIOR ASIC TIMING ENGINEER Job in Santa Clara, California Us
SENIOR ASIC TIMING ENGINEER #1397663RESPONSIBILITIES:- Timing signoff and convergence of large-scale high-frequency low-power ASIC or CPU designs at block level, cluster level, or full chip level.- Own full aspect of timing from RTL to gds2, including effective RTL coding/synthesis strategies, timing constraints generation, physical/timing convergence, and ECO implementation.MINIMUM REQUIREMENTS:- BS in Electrical or Computer Engineering + 5 yrs experience in Timing- Hands-on expertise and experience in full-chip Static Timing Analysis, timing constraints generation and management, and timing convergence Read more […]
June 6, 2009
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